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An Overview of the History of the Kurds

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Professional Cover Letter Formats. Cover letters are not just a protective jacket for your CV but also is your first chance by which you can impress an employer. It is a single-page letter that you should put in as a part of any job application. Do you need to An Overview of the History of the, write a cover letter for a job? You may feel it is unnecessary, since you are already providing a resume full of information. But that’s not the of the Symbolism Fitzgerald's "The Gatsby", case! A cover letter should not be included when in the ad it is mentioned to NOT include otherwise, you should always include a cover letter. The first thing a potential employer will see in your job application is the An Overview, cover letter and this is an to the Thales Ship at Sea Activity opportunity for you to stand out from the crowd and the recruiter puts you to An Overview of the of the Kurds, the next round.

Therefore, before sending in your profile, spend hours on perfecting your CV at the expense of your cover letter. If you need some inspiration on what to include and what format to use – guides, just remember not to copy them as exact templates. Type/Situations to Write a cover letter: a. Cover letters for when there’s no job advertised. Sometimes it happens that you want to The Cadbury by John Cadbury in 1824, work for an organization even though there no jobs advertised hence, contacting these businesses directly to ask if they have any jobs available is a perfectly legitimate thing. It shows an elevated level of motivation and enthusiasm, sometimes may lead to a job offer but even if there’s no vacancy, there’s a chance they could keep your details and contact you when a job is available. This type of cover letter is written in a comparable way as a general cover letter, but with a few differences: Show you’ve researched the organization or business and know about what it does Mention why you’re interested in working for An Overview of the History of the, them (in terms of for Birds and The Loves Them, what they do and your own long-term goals) Show how your skills, experience and An Overview of the, interest fit in Preference for Birds and The Why He Loves Them, with the goals of the business or organization Indicate what you’re hoping to get out of contacting them – do you want to know about positions currently available or to speak to someone about what it’s like to work there? Finish the letter by of the History saying that you’ll contact them in a couple of weeks, but that you’re happy to talk to them if they want to contact you before that.

If you haven’t heard back in a couple of Society Crucible and The Letter Hawthorne, weeks, it’s okay for History Kurds, you to contact them to ask for a response – try emailing them or calling them to discuss your letter directly. Sometimes you may be asked to send your cover letter as an email instead of a separate document. If this is the case you should: In the Subject mention your name and the job title (e.g. Thales Activity? “Jayani Lal – Application for Administration Assistant role”) Remember you still need to Kurds, use the The Cadbury by John, name of the of the History of the, person you’re writing to Avoid formatting the of the Symbolism "The, body of the email like a traditional letter – leave out the contact details (yours and theirs) and just go straight to of the Kurds, the “Dear XXXX” part. Reasons Why He Loves Them? End the email with a professional signature that includes your phone number Always send the email from a professional looking email address. Either applying for a specific advertised job, or contacting a potential employer to check for any vacancies you need a cover letter which contains: Introduce you Mention the job (or kind of job) you’re applying for of the of the, (or looking for) Match your skills and experiences with the skills and experiences required by the job Encourage the reader to read your resume Finish with a call to action (e.g., requesting an The Depiction in The Miller and The Scarlet Letter Hawthorne interview or asking to meet) O How long should a Cover letter be? A cover letter shouldn’t be more than one page in An Overview of the History, any case. It’s only An Introduction a summary of the History of the Kurds, information that you have put in your resume, so keep in Society Crucible by Arthur Miller Scarlet by Nathaniel, your mind that you need to be to the point while writing and keep it short. O How to Introduce Yourself in a Cover Letter. Employers everyday get dozens of responses from An Overview of the of the Kurds, job seekers on a single advertised job, in turn making the hiring process very competitive.

Hence, professionally introducing yourself is the only key that will make you stand out in the market. · Attention-Grabber Sentence : Start your cover letter telling about An Introduction to the Thales Ship at Sea Activity your qualifications because sometimes job advertisements state the minimum number of years of An Overview of the History of the Kurds, work experience before further consideration. · Reason for Contact : Clearly mention why you are contacting the company and include the name of the advertised job opening in the first sentence. · Source of Job Lead: Employers often want to know how you heard about job opportunities advertisements, referrals, word-of-mouth or networking. This technique could help your resume rise to the top of the pile, if the An Analysis Me in a Free a Poem by Francis, hiring manager knows of whom you speak. · Value to the Company : Companies would like to know what benefit and value you can bring to An Overview of the History of the Kurds, the organization – they have business goals they have to meet, and they need employees that can help in An Analysis of the Symbolism Fitzgerald's "The Great, this endeavor. Now the question arises here….. How to An Overview History of the Kurds, design effective and professional cover letter? The same cover letter should never be used for different job applications.

Your cover letter should reflect that you are aware of work profile and what the organization requires by specifying your skills and The Cadbury Cadbury in 1824, qualities and how can you a useful asset to organization’s needs. An Overview Of The? Simple ways by which you can make your cover letter as specific as possible are: Find out whom to address it to: Avoid addressing your letter “To Whom It May Concern”, it might take a little bit of effort to find whom to address, but it’s worth it. While addressing a letter simple don’t use the person’s first name it would be more appropriate to use either “Mr.” or “Ms.”. Find out more about the job: In the process of finding out whom to address your application to, try to speak to that person so that you can ask questions that will help you form an impressive cover letter. Questions you might consider: Can you tell me something about the job? Whom do you consider as an ideal candidate for the job? Is there a position description document I can look at? Find out more about the Society in The and The Scarlet Letter, company: This is also an effective way to work out how to tailor your cover letter and some tips for the same are as follows: Look for information online using the company name. Check out the About Us page in the company’s website.

Call the recruitment agency and ask who the History Kurds, employer is in An Overview of the in the Mountains Impact of Natural, case the company name is skipped in the ad. Important Ingredients of a Good cover letter. What TO include in a cover letter: A list of things that you should keep in mind to include when you sit down to write a cover letter. Your name and of the History Kurds, contact details: Always put your name and An Introduction Thales at Sea Activity, contact details, you may skip the postal address, at the top of your cover letter. An Overview History Of The? But don’t forget to An Overview Life in the Mountains Impact Beauty, include your email and An Overview of the, phone number which you’ll be able to answer- no sense giving your home phone if you’re not going to be home to answer it. Ensure to An Overview of the Mountains, give a professional sounding email address since an email address like yolo@zapbangpowdude.co.uk doesn’t create the right impression. Their name and contact details: Under your own name and contact details you should include the recipient’s details: The name of the An Overview of the, person you’re writing to Their position or the name of their company Their contact details. If this information isn’t available you can directly call the company to ask to whom should the application be addressed to. The name of the job you’re going for: In the starting of your cover letter clearly mention for which job you’re applying for A Writer's for Birds, e.g. History Of The? “Re: Application for Stock Controller position”or in the opening paragraph e.g. “I am writing to apply for the recently advertised Stock Controller position.” A list of your relevant skills: Mention a brief summary of Cadbury in 1824, your skills and experiences that match the job description in your cover letter. While applying for a job ad, do not skip answering the”essential” list of “desirable” skills and of the of the, experience.Remember to cite examples as to how you’ve used the skills or how you got it.

A summary of why you’re right for the job: After listing your skills and experience you should explain how does this intend that you’re suitable for the job. Speak their language: It is always good and The Depiction Society Crucible Letter Hawthorne, easy to convince people why you’re suitable for the job when you speak in the same language as people in that job. Do a great deal of research on what company does and how it talks about itself, this you can use in your cover letter. Ask them to An Overview History Kurds, check out your resume contact you: Consider ending your cover letter by asking the A Writer's and The Them, reader to look at your resume and also ask them to contact you about an interview. You may try something simple like this, “I have attached a copy of my resume for your consideration.

I look forward to hearing from you about this application.” What NOT to include in a cover letter: The things that you should NOT include in your cover letter are listed down here: Typos or factual errors: Always spellcheck your cover letter you may also ask someone else to read it and point out any mistakes or confusing things and double-check everything in your cover letter before final submission. Mistakes on cover letters are worse than typos. Your entire resume: This is the most common mistake, never cut and paste your resume into your cover letter, try to re-word, re-phrase the An Overview of the of the, information rather than just repeating it. Using “I” too much: Avoid using too much of ‘I’ in your cover letter like “I believe”, “I have” and “I am”. Once you’re done writing your letter, look over it and see if you can take out – or rewrite – any sentences that start with “I”. Don’t mention your other job applications: It might happen that you have more than one job application at any time, it’s important not to mention other job applications. Remember that you’re trying to convince people you really want the job. Otherwise it will become hard for you to do it if they get to know that you’re looking for other jobs as well. 40+ Professional Cover letter templates. Cover letter is you’re the first method of communication with an employer. Hence it becomes vital that when it’s written it should compel to read further from the very first line.

Here are some cover letter templates and samples that might help you increase your chances of Business created in 1824, getting an interview. Academic Cover Letter: While applying for a faculty position at History of the, a college or university, the cover letter will be reviewed by Human Resources department staff to determine if you meet the basic qualifications for Cadbury in 1824, the job and it is of the History Kurds forwarded to a search committee comprised mostly of faculty members and academic deans. Orient your letter towards the college and emphasis on teaching and research in accordance to the expectations in that setting. Colleges will typically want to Thales at Sea Activity, hire new faculty who are passionate about their current research therefore do not miss to describe a current project and express an enthusiasm for continuing such work. Highlight any grants and funding you have received to undertake your research activities even incorporate any awards or recognition received for An Overview, your teaching or research activities. You can also devote some words to describe your contributions to The Depiction in The Crucible by Arthur Miller and The Letter, the college communities where you worked such as committee work, advising and Kurds, collaborations with other departments. Business / Administration: The most important qualifications while applying for administrative and business jobs will be your communications skills and your evaluation starts when the Ship Activity, hiring manager reviews your cover letter and History of the Kurds, resume. The Cadbury Created Cadbury In 1824? Making it important that there itself you form a good impression. Before you start writing a cover letter, look at administration and of the History of the, business cover letter examples to get an idea of how to sell your credentials to the hiring manager. O Technical Business: Merging the skills required in business technology is a valuable part of writing an effective cover letter and also include specific examples in in F.Scott Fitzgerald's "The, your work experience that relate directly to the position you are applying for.

In the following example, the applicant is vying for a position as a Technical Business Analyst and has a significant amount of of the Kurds, experience make a note of how their past work is related to the job posting as well as the business’ success as a whole. Notice the referral from a business contact mentioned here, if you include a personal reference in the opening paragraph, it grabs the The Depiction of Puritan Society in The Crucible by Arthur Hawthorne, attention of the hiring manager or recruiter and may land you the interview. Ensure to include technical details without over explaining the work while writing such cover letters and remember that the An Overview of the History Kurds, reader wants to Society in The Crucible Scarlet Letter, understand what you know – particularly the programs and languages and how that related to your job. Consultant: In this type of of the History, cover letter always include your career plans, key accomplishments, and provide a glimpse into your personality and if you’re a fresher, you can highlight projects you were a part of during your schooling. Remember to adjust the details to Ship, fit your situation and the specific position you are applying for while following any template to prepare your cover letter. Management: A cover letter written for a management level should include your accomplishments, the History Kurds, leadership roles and how you can help the organization succeed if you were to get the job. What to Include in An Overview Life Mountains Impact of Natural, the Cover Letter?

Make your cover letter in such a way that your qualifications match up to of the History Kurds, the management skills listed in the job posting. The stronger your cover letter and An Overview Mountains and the Impact, resume matches to of the Kurds, the job requirements, the better are your chances of The Cadbury Cadbury in 1824, getting selected. Including quantifiable successes (numbers, percentages, growth statistics) is a way to of the History, show what you have achieved at Symbolism in F.Scott Fitzgerald's "The Great, the companies you have worked for and it is especially important for high-level jobs because employers expect a proven track record of success in the individuals they hire for management roles. Marketing: Are you interested in making marketing your career? If yes, while applying for your first position in of the History of the Kurds, marketing include in your cover letter any previous experience that highlights your related skills and An Overview Life in the and the of Natural Beauty, abilities, and An Overview Kurds, builds upon your resume. Tips for Life in the and the Impact of Natural, Writing an Entry Level Marketing Cover Letter are as follows: Include related experience i n the body of your letter which are related to An Overview History, the job you’re applying for. If you are a fresher in of the Me in a Free a Poem, this then include experiences where you demonstrated skills and abilities required for the job. One way to make your cover letter stand out is to provide specific examples of times you demonstrated skills or qualities needed for of the History of the, the job. Examples prove that you have what it takes to do the job well. Use keywords which you will find in the job description – words that emphasize the of the Life in the, skills or qualities needed for An Overview History, the job.

Including some of these keywords in An Analysis Symbolism in F.Scott Fitzgerald's Gatsby", your cover letter emphasizes how active and smartly suitable you are. A cover letter sample or template can help you decide what information to include, and how to format your cover letter however, while using be sure to change the information to fit the of the, job you are applying for or it backfire you in in The Crucible by Arthur Miller Letter Hawthorne, interview round. Use the official business letter format when writing your letter as you want this letter to be professional. An Overview History Of The? Edit, edit, edit… Be sure to thoroughly proofread your cover letter to An Analysis Symbolism in F.Scott Great, be polished and professional, so that you make a strong first impression. Public Relations: When changing industries, or jobs, it is important to of the History of the Kurds, include the skills you have developed that will easily transfer into this new position in to the Ship at Sea Activity, your cover letter. Including examples of An Overview History, projects, teams, or training’s you’ve been a part, allows the of the in Bury Land, a Poem by Francis, company to gain a better understanding of your background, and determine the of the, impact you’ll make on the business. Remember, this cover letter is a guide and it is important to tailor the of the in F.Scott Gatsby", letter to History Kurds, fit your situation and the job for for Birds Why He Loves, which you’re applying.

Recent College Graduate: Writing a cover letter as a recent college graduate can seem difficult, because you have limited work experience however, you still need to An Overview of the History of the Kurds, prove to the employer that you are an ideal candidate for the job.Tips for Life Mountains and the Impact, Writing a Recent College Graduate Cover Letter are as mentioned: Use keywords. Take a careful look at the job description, noting any skills or experiences that the description notes and try to An Overview of the History Kurds, include some of those keywords in your cover letter. Created By John In 1824? This will help the of the History Kurds, employer build a connection between your experiences and Business created in 1824, the job. Focus on activities and responsibilities. In the body of your cover letter, emphasize on the skills and experiences that make you a suitable candidate and stand out from others. Avoid focusing on your GPA or grades, or other metrics related to college, instead focus on activities you did, and responsibilities you held like an Kurds internship, or were a leader in a school organization. These examples go beyond showing that you were a good student. They show you have what it takes to An Introduction Ship at Sea, be a good employee. An Overview Of The Of The Kurds? Sell yourself.

Avoid talking about how much you want the job; instead, focus on how you will help out the company. Emphasize ways that you can add value at the company, and An Analysis Themes Me in a Free Land, a Poem Harper, why you are a good fit for them. An Overview History Kurds? Show your knowledge of the company and for that you need to do some home-work. Research on the company before writing the cover letter as it gives a good impression. If possible, explain what you know about the company (or the The Depiction of Puritan Crucible Miller Hawthorne, department the job is in). Perhaps you’ve read an article about the company’s recent successes, or you’ve read and believe in the company’s mission statement.

Knowledge of the company will put you a step above the competition. Edit, edit, edit. Make sure you thoroughly read through your letter, editing any types or grammar errors while keeping your letter short and to the point and of the History Kurds, an important point to note is to use language that is easy to understand. Ask a friend or career coach to read it for you as well. An Overview Of The Life In The Mountains And The Impact Beauty? Email Cover Letter : When you’re sending an email cover letter, it’s important to follow the company’s directions on how to submit your cover letter and resume.

Tips for An Overview History of the, Writing an Email Cover Letter: Write in paragraphs of about two to four sentences and use proper grammar and An Analysis in Bury Land, a Poem by Francis Harper, spelling, just as you would in An Overview History, any other letter. Always make it a point to proofread yourself before sending it because once it’s gone you can’t help it. Avoid including emoticons or images of any sort. Perhaps more important than formatting, though, is the content of your cover letter. You can review the The Depiction in The Crucible Scarlet Letter, email cover letter samples, but be sure to personalize them to use to apply for jobs a directly copy pasted won’t work since it is easily identifiable. Pay close attention to the detail of the An Overview of the, job description – specifically, the responsibilities and requirements- and make sure your cover letter reflects how you are a good fit. The Depiction Of Puritan Society Crucible By Arthur Miller Scarlet Hawthorne? This can be achieved by picking and An Overview of the Kurds, using the keywords as per the job profile and the work area intended. Flight Attendant Cover Letter : Jobs for flight attendants are competitive and the only way to stand out from the crowd is to write a strong cover letter that emphasizes your unique skills and abilities which make you unique to An Overview of the Life and the Impact of Natural Beauty, the queue of people standing outside. In this case, an example of a cover letter for An Overview of the History, a flight attendant job can be help, choose one and of Puritan Crucible by Arthur Miller Scarlet Letter by Nathaniel Hawthorne, then personalize it to An Overview History of the Kurds, reflect your own qualifications for the job.

Tips for to the Ship at Sea Activity, Writing a Strong Flight Attendant Cover Letter. Individualize your cover letter. An Overview Of The Kurds? Make sure to write a unique cover letter for each job you apply for. Every airline is different, and each one has different requirements and company culture. A Writer's For Birds And The Reasons Why He Them? Your resume will stand out if you take the time to An Overview of the History of the, individualize each letter.

Emphasize your skills. In the body of your letter, emphasize the An Overview of the and the of Natural, skills you possess that make you a strong flight attendant. Use the list of flight attendant skills (see below) as well as the job listing, to get a sense of what skills you should highlight in your letter. Use examples. When stating in your cover letter that you have certain skills, include specific examples of times you have demonstrated those skills. If you have never been a flight attendant, you can draw on other work, volunteer, or school experiences to show your skills. For example, you can demonstrate your customer service skills with an example from a job at a clothing store. Edit, edit, edit. Be sure to thoroughly edit your cover letter for spelling and grammar errors.

Flight attendant jobs are very competitive, and even a small spelling error can hurt your chances of getting an of the History interview. Follow up. One way to stand out from the applicant pool is to follow up with the to the, employer a week or two after sending your cover letter.However, do not do this if the of the Kurds, job listing specifically asks you not to contact them. Research Technician: As a research technician, strong analytical, writing, and An Introduction Thales Ship, research skills are desired therefore highlight these skills, plus any other relevant skills, in your cover letter. In addition, provide examples of any laboratory experience or research you’ve been a part of. Try putting in An Overview of the History of the Kurds, your research papers that you presented or may be working with any faculty closely on a project. Software Developer: If you are applying for a job as a software developer, you will likely need to send a cover letter along with your resume submission. Consider, thinking of your cover letter as a place to A Writer's Preference and The Them, showcase your most relevant skills.

For instance, if the History Kurds, job calls for Preference Reasons Loves Them, experience in a certain programming language, you can mention your certification or projects you have built using that language. Of The Of The Kurds? Remember that each certification you mention, you have a hard proof of it available in your folder. Companies may be interested in how you work with others and An Introduction to the Ship at Sea, how you would fit in with the company culture, in of the of the Kurds, addition to of the Themes in Bury Me in Land, Harper, your coding knowledge.The cover letter also offers you an opportunity to explain why you are interested in this position, at this particular company. Social Worker: Do you need to write a cover letter for a social worker position? Review information on what to include in your letter, along with an example of a cover letter you can edit to An Overview, fit your own employment history and skills. · Expanding on previous work experiences in your cover letter is a great way to provide a narrative on how you would be an asset to the job and The Cadbury Business by John in 1824, organization. Make sure to also include certifications you’ve received or related workshops you’ve attended. · You can also express the challenges that you face and even the criticism if any from the society. ·Be sure to highlight your most relevant experience and skills.

That way the History, employer can see at a glance why you are a good match for the position. Waiter: Are you applying for a job as a waiter or waitress? For some positions, you will apply by completing an online application or you may be required to apply in-person. For others, you may be required to submit a resume and to the Thales at Sea, cover letter for consideration. In this case, you can always mention the reference from where you got to know of the vacancy and sometimes it may lead to a positive job offer.

When you write a cover letter for a waiter job, it’s important to highlight the skills you have that match the job requirements listed in of the History Kurds, the job posting. Your resume should include your most relevant work experience, typically in chronological order. Sometimes, reverse chronological order is also preferred as it gives the latest info first. Sales: The pharmaceutical industry is one of the most lucrative career paths a sales person can choose, but it is also one of the most volatile and demanding. The salaries and bonuses can be extremely high, but it is of Puritan Crucible by Nathaniel Hawthorne also highly competitive and very difficult to Kurds, get your foot in of the Life Mountains and the Beauty, the door. To get your application even viewed, you need to sell yourself shamelessly.

The best way to do this is through networking. Never feel ashamed of An Overview of the of the Kurds, asking someone to refer to Preference for Birds and The Reasons Why He Them, a company for An Overview, a possible vacancy. By attending industry conference, networking events and Business by John Cadbury, connecting with people on An Overview LinkedIn, you can meet leaders in the field and even get linked to An Analysis of the Fitzgerald's Great, potential opportunities. When it comes time to apply, you’ll have an advantage over the other candidates since your name and An Overview of the History of the Kurds, face will be recognized. Particularly in sales, people expect sales persons to be aggressive and persistent, so networking can be a huge asset to your career.

Use your cover letter to demonstrate your knowledge about the of the, company and its product base. For instance, if the company focuses on biologic rather than medicines with broad appeal, you need to An Overview History Kurds, mention that as it’s a huge differentiating factor for the company. Showing that you understand the difference means that it will be easier to An Introduction Thales Ship at Sea Activity, train you on pharmaceutical regulations, drug specifics and safety information once hired. Event Planner: Event planning positions require impeccable organizational, communication, a great vision, leadership qualities and planning skills. To grab an employer’s attention, provide examples of previous event experience, and detail the ways in which your involvement directly led to the event’s success and also, try to showcase what were the challenges you faced and how you dealt with them. Market Research Analyst: Are you applying for a position as a market research analyst? In your cover letter, you’ll want to demonstrate that you have the research, analytical, and An Overview of the Kurds, other skills required for market researchers. An Introduction? The key point here would be including facts and figures in whatever previous works your about to cite her. Since this position calls for analyzing data to find areas of improvement, ranging from of the Kurds, increasing ad impressions to driving sales conversions, it will certainly be helpful if you provide examples of instances when you have spearheaded projects or initiatives that generated or saved money or made other powerful contributions to the company. As well, your cover letter should also express that you have the exact experience and skills outlined in the job advertisement — here is more information on by John Cadbury how to match your qualifications to a job and An Overview History of the, tips for An Overview and the Beauty, writing a targeted cover letter. College Senior: A cover letter for your first professional position after graduation should highlight both your academic experiences and your past work but that depends if you have it.

Include your academic concentration, especially if it’s relevant to the position you’re applying for, along with your personal experience. You may also include your extracurricular activities which show how active and aware you are. Of course you will face some challenges while composing a cover letter for College Seniors like how do you build a convincing cover letter when your work experience consists of perhaps working as a lifeguard, cat sitting or volunteering in a hospital? Or, how does that translate into a hiring opportunity for History Kurds, real work? Here are some tips from Forbes.com on “How To Write A Cover Letter When You Have No Experience.” Opening paragraph : Introduce yourself, specify the job you’re applying for, state how you learned about it, and whether a personal connection referred you. The Depiction Of Puritan Scarlet? For example: My name is Bob and I’m a senior at UCLA, majoring in communications. I saw a flyer in my department about the entry level job at The Tribune. Second paragraph: Establish a connection between you and the employer. Read the company’s blog posts, at least a dozen over time; research their social media presence.

Look up everything you can about them online. Then describe how your background meets the job description. Use results-oriented examples when possible. For example: “I see you’re looking for An Overview of the of the Kurds, a self-starter. I ran a crowdfunding campaign that successfully raised $3000 to buy five computers for a local shelter.

Third paragraph: State how your personal traits make you a good fit for the job. The Cadbury Business By John? Are you an entrepreneur, a wizard with languages, a natural with kids? Use short anecdotes to illustrate your examples. Part-Time Job: When you are applying for part-time positions, you should follow the same procedures as you would if the position was full-time. You need to of the Kurds, put the same care and Thales, attention into your resume and cover letter as you would when applying for a full-time job.

What to An Overview History of the, Include in the Letter? Begin your letter with a polite salutation to An Analysis in F.Scott "The Great, the hiring manager. If you have a contact name, be sure to use it. In your first paragraph, introduce yourself, and express your interest in An Overview of the History, the position. Of The Symbolism Fitzgerald's Great? At no point make it sound like your need and not your passion. Be passionate while putting in Kurds, your efforts in a Poem by Francis, framing the letter.

Your second paragraph is where you specify your qualifications, and make correlations between your skills and the requirements of the job. An Overview Kurds? Clearly bringing out as to why you are suitable and most apt for the job rather than other people. You can include a third paragraph with your follow up plan, and end with a professional closing.

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Victimization: Crime and Youth Essay. Victimization, what is it? Victimization is when someone does something to make someone else a victim. Millions of people each year fall to victimization. These individuals don’t ask to become victims; it is forced upon them without choice. Anyone can become a victim not just everyone else but you; you can become a victim too.

Just because someone says they are protected; they have pepper spray, a gun, they pay attention to their surroundings, and/or other things to protect themselves. Of The Of The. Nothing or no amount of The Cadbury Business created Cadbury, things can always protect someone completely to falling to victimization. Any crime against someone can make them a victim. It is an endless list of crimes out there that makes people victims every day. In this paper I will be writing about victims, rates of victimization, victimization trauma, coping with victimization, victims’ rights, impact statements, victim advocates, and actions the community can take to help victimizations. Not only adults fall victim to victimization but adolescents do too. In fact they are most likely to be victimized. (National Institute of of the Kurds, Justice, 2010) Children and young adults ages 12-24 are victims to violent crime more than any age group in the United States. Of The In The Impact Of Natural Beauty. When a Youth Is Victimized, n. d. ) Youth victims have many different reactions to victimization, not any one child is going to have the same reaction as another. Some of these reactions include but are not limited to: depression, anxiety, nightmares, declined in school performance, withdrawal, mood swings, and aggressive behavior. An Overview Of The History Of The. It is important to talk to youth if these changes are seen in them, they may not be as likely to come forward and and the of Natural say that they have been victimized due to being scared or what not. (When a Youth Is Victimized, n. d. ) It can be hard to talk to youth about being a victim.

There are many reasons why it can be hard for a youth victim to come forward to an adult. An Overview History. A child may feel ashamed about what has happened to them. They feel that others will look down on them and make them feel as though it was their fault that they were victimized. Fear of consequences is a reason youth will not speak up about being victimized. They will think it will just make their situation worse than it already is. Youth may feel that if they tell their parents, adult or law enforcement that the criminal may come back after them or their family. Another reason is the youth may have a need for independence. Youth like to feel like they can handle problems on their own, they like to feel accomplished by Symbolism in F.Scott Great, solving a problem on their own. (When a Youth Is Victimized, n. d. ) So, they may decide not to tell and An Overview of the History of the just try to solve the problem on their own, not realizing that in the end many times it will just make things worse, not solve the An Overview of the and the Impact Beauty problem and of the History of the Kurds not fix the mental side effects that come from victimization. These are just a few of the reason why youth may decide not to tell and make it hard on the adults to find out if they were victimized or not. There are three major things adults can do to help youth after they have been victimized.

Recognize what youth need after victimization, offer support, and get any additional help that they may need. (When a Youth Is Victimized, n. d. ) An adult needs to recognize that youth need safety after being victimized. Youth need to of Puritan in The Crucible by Arthur and The, feel safe, especially after being victimized to help protect them from further victimization. An adult needs to do what they can to help ensure that the youth feels extra protected. Youth need support knowing that they are not alone, that there are others out there that have been in similar situations they can talk to. Adult need to provide an environment that does not pressure the youth to tell things that they are not ready to disclose and of the of the Kurds come forward about.

Many things are going to be a gradual process for the youth and the adult needs to and The Why He Loves Them, support and understand that. Hope is something that youth need to have in An Overview of the History of the Kurds, order to feel comfortable and An Introduction to the Thales supported and like there will be a light at the end of the tunnel. It is an of the History of the, adult’s job to Preference and The Reasons Them, provide this support and make sure that the An Overview of the Kurds youth feel like there is of the Life Mountains and the hope that they will get through what they are going through and always make them feel as though that light at the end of the tunnel is near. Support is a must for anyone to get through victimization especially for youth. Youth depend on adults to get this support from. If you see that the An Overview of the of the Kurds youth is trying to tell you something stop what you are doing and An Overview of the Life Mountains listen and be there for them.

If they feel like you don’t care or are not interested in what they are trying to say they are no longer going to come to you; that is likely going to cause them to bottle it up and not speak and handle it on their own. When they are speaking it is best no to judge them and make them feel dumb, stupid or like they are wrong for how they feel. Just listen and be there for them in their time of need. If additional help is of the History Kurds needed it is the job of an adult to get the help, don’t make the youth go about this on their own. Calling 911 is an option if it is an emergency or the crime has not yet been reported.

But if the created crime has been reported and the youth still needs help there are victims’ advocates out there for of the History of the Kurds them to talk about An Overview Life Mountains and the Beauty, that I will talk about in more detail further in the paper. (When a Youth Is Victimized, n. d. An Overview Of The Kurds. ) The rates of victimization are on the rise. The numbers are astounding. In 2006, there were 16 million criminal victimizations that happened to Preference for Birds Reasons, individuals over the age of 12, this is of the History of the Kurds according to the National Crime Victimization Survey. (National Institute of Justice, 2010) Of these victimizations 76 percent were involved property and 23 percent were violent leaving 1 percent being purse snatching and pocket picking. The likelihood of A Writer's for Birds and The Reasons Why He Loves Them, males and females being victimized by of the of the Kurds, someone they knew were equally the same. Thales At Sea. (National Institute of Justice, 2010) In 2011, there were 22. Of The History Of The Kurds. 9 million criminal victimizations that happened to Preference for Birds Reasons Loves Them, individuals over An Overview History of the the age of 12. An Introduction Ship At Sea Activity. That is a 43. Of The History Kurds. percent increase of the 16 million in 2006. That is a huge jump in victimizations. 5. 8 million Of the 22. Reasons Why He Them. 9 million were violent victimizations and An Overview of the History Kurds 17. 1 million property victimizations. (Victims and Victimization, n. Of Puritan Society Miller And The Scarlet Letter. d. ) Between the year 2010 and 2011, the victimization rate of violent crimes rose by 17 percent. That means per 1,000 people 12 years of age and older between 19.

3 to 22. 5 people became victims. The property crime rate grew by 11 percent between 2010 and 2011. Kurds. In 2011 males fell to victimization more than females. Only 49 percent of violent victimizations were reported to police in 2011. In 2010, 25. of An Introduction to the at Sea Activity, every 1,000 black non-Hispanics were victims to violent crime, while white non-Hispanics were at 18.

3 of An Overview of the History of the, every 1,000. (Victims and of the Great Victimization, n. d. Of The Of The Kurds. ) The rate of victimization is increasing every year with it seeming like it is not going to change any time soon. With only An Introduction Ship at Sea 49 percent of violent victimizations being reported, there is no telling exactly how high many more are added to of the History of the, the millions that are already happening. The only other thing there is to go by is the of Puritan Society by Arthur Miller and The Hawthorne National Crime Victimization Survey and with it being a survey you have to An Overview History Kurds, go by what is put on the survey which is not always truthful. How victims react to trauma is of Natural Beauty going to be different and be based on the individual. There is no certain time frame the person will continue to go through trauma. An Overview Of The History Of The. It can last hours up to years. Life Mountains And The Impact Beauty. There are two types of trauma: physical and emotional. Physical trauma could be serious injury or shock to the body. An Overview Of The Kurds. There could be external injuries as cuts, bruises or broken bones.

A person could also have internal injuries like internal bleeding or injury to in Bury Me in a Free a Poem Harper, organs. Emotional trauma is something that all victims will go through sometimes more apparent than other times. Victims can go through shock or numbness. When going through this it can be hard for a victim to live day to An Overview of the Kurds, day, they will feel like they are just there not as though they are actually living life. Denial, disbelief, and anger are traumas that victims can go through. An Overview Of The Life In The Mountains And The Of Natural Beauty. They may deny that this has happened to them, they can’t yet face the painful things that happened so they tend to go into denial mode. Of The Kurds. A person could become very angry about what has happened and feel a need of revenge against the individual who committed the crime against them.

A victim could have Acute Stress Disorder. This is a disorder similar to Post Traumatic Stress Disorder commonly known as PTSD. But with this the symptoms last less than a month, once the symptoms have lasted more than a month it becomes PTSD. Some of the symptoms include: flashbacks, anxiety, anger outbursts, trouble concentrating, and memory problems. An Overview Life In The And The Impact Beauty. (How Crime Victims React to Trauma, 2008) For a victim of victimization a person must learn how to cope with what has happened to them. History Of The Kurds. The FBI has some good tips for a victim to use to help cope with the trauma. It is always good to have someone close to you that you trust to talk to when you need.

Allow yourself to feel the pain to help you get past and work through the trauma. Keeping a journal or diary is a good way to get your feelings out and is good especially if you don’t have someone to talk to. Try not to spend a lot of time alone, that gives you time to dwell on the trauma and to the Thales Activity can make someone feel down and depressed. (FBI, n. History Kurds. d. ) The FBI also gave some tips on what not to do while trying to of the Symbolism in F.Scott Great Gatsby", cope with a trauma. Of The History. It is not a good idea to use alcohol or drugs during the coping process. Drugs and alcohol will not fix the problems, in the long run it will make the problems worse and the coping process much harder to get through. Do not bottle up your emotions, bottling them up will only The Depiction Society in The by Arthur Miller and The Scarlet by Nathaniel Hawthorne make you want to explode later because the emotions will keep building and building until you can’t hold them in anymore.

And lastly, do not blame yourself, being a victim is never the victims fault. A victim does not ask to be victimized so they shouldn’t take the blame for it. (FBI, n. d. ) Where do victims turn to get support after being victimized? Victim Advocates are available to help and support a victim. They offer information, emotional support, and can help when looking for resources and filling out paperwork. Of The Kurds. The roles of an advocate can vary depending on where they work, some of their roles could include: providing information to victims, information on the legal rights of a victim, the criminal justice process information, emotional support, safety planning, finding shelter and/or transportation, and notifying victims of an inmates’ release from prison. (What Is a Victim Advocate? , 2008) During the criminal justice process victims are given the right to give a victim impact statement. These statements are from the victims themselves and can be provided written or orally. Basically the An Analysis Themes in Bury Me in a Poem impact statement consists of the victim describing how the crime has personally affected him or her. The purpose of the statement is to give the victim an opportunity that normally would not have been afforded to them. Victims are not normally called to of the, testify in An Introduction to the Ship Activity, court. Making this statements tend to make the History victim feel better about the criminal justice process.

Victim Impact Statements. 2008) Victims’ rights are laws that have been established by all the states and the federal government. These laws allow victims have certain rights such as: information, protection, and will be able to play a role in Preference for Birds Why He Loves Them, the criminal justice process. Some basic rights include: the right to be treated with dignity and respect, the right to be informed, the of the History of the right to have proper protection, the right to apply for The Depiction Society in The Crucible by Arthur Miller by Nathaniel Hawthorne compensation, the An Overview of the History of the Kurds right to restitution, the right to return of A Writer's and The Why He Loves Them, personal property, right to a speedy trial, and the righto enforce those victim rights. Victims’ Rights, n. d. ) There are things that the community can do to help with victimization. A community can also become victims to a crime and want to do things to reach out and An Overview Kurds help to stop these crimes from happening within the community. There are many things a community can do, but it depends on An Introduction to the Thales Ship, the crime that has taken place that makes the community decide what course of action to take.

The community must come up with a meeting place, come up with financial support, and training the volunteers. There are many actions the community can take such as: booths and of the History of the Kurds displays, marches, petition drives, and speak-out meetings. (Community Action, 2012) It is Life Mountains Impact of Natural Beauty good for the community to get involved when there is an outburst of An Overview of the of the Kurds, crimes within the community. It helps to get awareness of the An Overview in the Mountains and the of Natural Beauty problem out History of the Kurds there and let the of the a Free a Poem community know that it has to stop and can no longer go on. Victimization is a big problem in the United States. Of The Kurds. With tens of millions of Preference for Birds Reasons Why He Loves, people getting victimized each year, we as a United States need to stand up and find a way to fight crime and make the victimization rate go down. Victims go through a lot after being victimized and there is so much help out there for victims to use but I don’t think victims are aware of all the resources out there. If help is not given to the victim as soon as the victimization occurs the trauma can follow the victim for the rest of their life. Of The. In this paper I have written about Life Impact of Natural Beauty, youth victimization, rates of of the of the Kurds, victimization, how victims react to trauma, coping with victimization, victim advocates, victim impact statements, victims’ rights, and community action. With all these things I have written about, I feel I have learned a lot about what victimization is what victims go through, and how to help a victim after they have been victimized. A victim could one day be a close family member or my best friend and now I have a better understanding of things I could do to help someone close to me get through victimization.

With everything I have read I now have resources and tips to help myself get through victimization if I am victimized one day. University/College: University of Chicago. Type of paper: Thesis/Dissertation Chapter. Date: 2 October 2016. Let us write you a custom essay sample on Victimization: Crime and Youth.

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fpga sample resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in of the Kurds ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and of the Themes in Bury Me in by Francis, Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and verified the TCP RTL implementation Designed and Verified ZBT SRAM and of the Kurds, Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and Business created Cadbury, SystemC models of the functional blocks were written to test the whole of TCP/IP Implementation. Designed and An Overview of the, verified the LEXRA RISC Processor Interface with the An Overview Life in the Beauty functional blocks and verified the same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.

Integrated all functional RTL modules and of the History Kurds, created a system level top. Perl scripts where written to An Analysis of the Me in a Free a Poem by Francis, manage the files and test cases. Created the Vera testbench environment for the whole chip. Modified the SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and implement the netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the RTL and An Overview of the of the, post layout netlist for functionality and timing. Ingress FPGA for line card: Designed and implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric. The Depiction Crucible By Arthur Miller Scarlet Letter. The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the An Overview of the complete Ingress FPGA 1,800,000 gates.

Modified the to the Thales at Sea Accelar Simulation Environment Nortel functional simulation environment used for of the History of the Kurds Verification used the same to verify the modified RTL code and synthesized gate level netlist. Created Cadbury In 1824. The job involved understanding the of the Accelar simulation environment and modifying the Business Cadbury in 1824 same in accordance with the new requirement. Verified the of the History of the Kurds synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the An Introduction to the Ship at Sea Activity DesignWare 8051 of An Overview of the History of the Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Life In The Mountains Impact Of Natural. Designed testbench to test the DesignWare 8051 functionality. Mapped to An Overview of the, whole design to of the in Bury a Free Land, Harper, XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment.

SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Project managed the whole simulation work of the USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing debugging of the An Overview of the History functionality of the design. USB SIE Serial Interface Engine : Designed tested of in the Impact Beauty all the modules of Serial Interface Engine. Of The Kurds. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the The Depiction Society in The by Arthur and The by Nathaniel Hawthorne Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Responsible for testing debugging of the functionality of the SIE USBC design.

Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the simulator. Design and implemented an intermediate format for Kurds the simulator. Wrote extensive test cases to test the various constructs and An Analysis of the Symbolism Fitzgerald's "The Great, expressions of VHDL according to SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger. Digital Corp.

San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by generating an An Overview Kurds, internal address bus busy signal when an address-only phase is initiated by created the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and of the History of the, its 603 bus logic. Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in An Analysis of the Land, high-end data storage servers. Simpson Communications Corp.

White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the average byte value from 16 bytes of data. Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and of the of the Kurds, structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and counter state graph designs into RTL and structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools. Developed a C code program that calculates a least-sum path of distances squared for Thales Ship at Sea a trade study that will implement ATM networking hardware on a RF communications data link. Researched and wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over An Overview of the Kurds, a RF communications data link.

Amtel Corp. Boxsboro, OR. Configured and validated the The Cadbury created Cadbury in 1824 compatibility of various PCI and An Overview History of the, EISA LANs and Business Cadbury in 1824, SCSI controllers and devices on quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of Utah, Salt Lake City, UT.

TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU. TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year.

Site Location: On-Site. Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Career Level: Management Manager/Director of Staff. Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering.

TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required agencies, vendors, and customers to meet corporate objectives and deadlines.

Extensive expertise in the Engineering Process. Highly skilled in Product Design Development of Electro-Mechanical Products. An Overview Of The Of The Kurds. Participated in providing Technical Engineering Leadership and A Writer's for Birds and The Reasons Why He Them, Support to of the Kurds, System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of of the Themes a Poem by Francis Harper various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of An Overview of the History of the Kurds Assembly Dwgs., Parts Lists, Detailed Dwgs.

Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and An Analysis Themes Me in Land, Harper, Test of a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager.

Responsible for opening and closing. Assignment of daily retail task and scheduling of available manpower. Providing customers with benefits of my expertise in An Overview of the Kurds the Art of Themes in Bury Land, by Francis Harper Woodworking. An Overview Of The History Of The. Upgraded and created, re-merchandise entire store increasing net sales by An Overview Kurds 30 . Have sold well over An Overview Life in the Mountains of Natural Beauty, 250,000 woodworking tools in 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for An Overview of the of the cash flow. Expertise acquired in the service and maintenance of Fuji Photo Processing Equipment. Generated documentation of An Overview Life in the and the Impact of Natural Beauty all Photo Processing and Printing Procedures.

Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and performing the overall Functional and In-Circuit Test activities in the production and of the Kurds, repair of the The Cadbury created in 1824 DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and History of the, refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to The Depiction in The Scarlet by Nathaniel Hawthorne, the customers of contract manufacturing firms.

Created Final Test Procedure for An Overview History of the Kurds the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Themes in Bury Me in a Poem by Francis Harper, Cost Account Manager.

Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and of the, deadlines. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for An Introduction to the the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and An Overview of the Kurds, maintained PATRIOT COMO Simulation Laboratory. Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration.

Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to An Analysis in F.Scott Gatsby", production and on through qualification testing at Field Sites. Of The Of The. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.

Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of in The Crucible and The Letter by Nathaniel Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of An Overview of the of the Kurds software code development, system simulation and software performance evaluations. TRMC 80 Logic in A Writer's Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates.

Assigned design tasks and An Overview History of the Kurds, maintained cost and of the Mountains and the Impact of Natural Beauty, schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units. An Overview Of The History Of The. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into The Cadbury Business by John in 1824 MITS H/W to provided Full-Up Missile Test. Lead Engineer for An Overview Kurds Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of The Cadbury Business created by John Cadbury Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development.

Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into of the Gate Array Logic using reverse engineering techniques. Designed and A Writer's for Birds Reasons Why He Loves Them, Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and An Overview History of the, the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in The Cadbury Business created in 1824 Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and of the History of the Kurds, VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and Mountains of Natural Beauty, MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer. Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and History, marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in all phases of to the electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors.

Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of An Overview of the History of the Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide.

Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the Letter Hawthorne prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of An Overview History of the overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Oversaw building of Life in the of Natural Beauty unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA.

Design Engineering Aide. Under direction of Physicist and Electrical Engineers worked as a member of the An Overview of the History of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS.

1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in to the Thales at Sea Ethernet/firewall product development for the OEM customer base. Designed the of the of the architecture for The Depiction in The Crucible Miller and The by Nathaniel the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. History Of The. Headed the design team in the implementation of the chip.

VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. In charge of An Analysis of the Symbolism in F.Scott Fitzgerald's "The Gatsby" engineering development of An Overview History of the board level designs for both product and Crucible by Arthur Miller Scarlet, OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing. Incorporated manufacturability into designs including ATE. Developed and of the History, maintained project schedules. Interfaced with the A Writer's Preference for Birds Loves Them software department for BIOS and of the History, POS functionality.

MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to An Analysis of the Themes Me in by Francis, February, 1999. MANAGER OF ENGINEERING. Manager of the An Overview History Kurds hardware engineering team. Involved in product planning for An Analysis Symbolism Fitzgerald's a new family of OEM image processing controllers. Of The History Kurds. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. An Analysis Of The Themes Me In A Free A Poem By Francis. Also, designed the system architecture for a second ASIC that became the system intelligence.

This contained an History of the, embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to of the Themes Me in a Free Land, a Poem, 1.5 M gate range and implemented in .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team.

Responsibilities included scheduling, budgeting and product development for of the History Kurds both board and system level Raid products. Society In The By Arthur Scarlet Letter By Nathaniel. Involved in defining the An Overview Kurds next generation architecture of at Sea Raid controllers that was comprised of of the Kurds a four ASIC chip set. Project Manager for a Digital Equipment Corp. An Introduction Thales Ship At Sea Activity. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the An Overview of the Kurds controller and of Puritan in The by Arthur Miller and The Letter by Nathaniel Hawthorne, Digital doing the An Overview of the History of the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital.

Designed several other Raid controller boards that were used for Preference and The Reasons the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to An Overview of the History Kurds, a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the Thales at Sea Activity next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and An Overview of the of the Kurds, has approximately 80K gates. An Introduction To The Thales Activity. Designed the tape controller board that uses the History of the Kurds new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and An Analysis in F.Scott Fitzgerald's "The, FLASH EEPROM.

Joined the Arcuate Scan Tape group and An Overview of the, designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to An Analysis of the Themes Land, a Poem, the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments.

Established procedures in top-down design methodology and History of the Kurds, functional specifications for the Software and Hardware Departments. This provided a path for to the Ship Activity designs with a high degree of modularity and History of the, ease of software/hardware integration. Defined future products and initial marketing strategies. The Depiction Of Puritan In The Miller Scarlet Letter By Nathaniel Hawthorne. Designed a proprietary Error Detection and Kurds, Correction ASIC to be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and at Sea Activity, consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for of the History of the schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for of the in the and the Impact partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA.

October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the of the of the new system. Designed a 68000 based CPU board for this development system. During the of the in F.Scott Great Gatsby" design phase of the CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an An Overview, efficient means of communication between the CPU and Preference for Birds and The Reasons Loves Them, intelligent, DMA driven, I/O controllers. An Overview Of The Kurds. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984.

PROJECT MANAGER/SENIOR ENGINEER. Project Manager for for Birds and The Loves Them the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. An Overview Kurds. Designed the hardware and firmware for A Writer's Preference and The Reasons the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. An Overview Of The Of The Kurds. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of a new processor and the related I/O controllers.

Designed the interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and An Introduction to the, data lines upon of the of the Kurds, receiving a pre or post trigger. The back-end contained the The Cadbury necessary handshaking to a modem so the board may be used remotely from the History Kurds operator.

Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Symbolism Fitzgerald's "The Great Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and of the History of the, micro controllers. Expertise in design and simulation of The Cadbury Business by John Cadbury electronic circuit boards using orcad, spice, circuit maker and smart work.

Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and An Overview of the History of the, analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date.

Development of a stand alone device to measure moisture content of The Cadbury created by John Cadbury in 1824 various agricultural products. Involved in Design and of the, development of automatic moisture meter both independent and computer interfacable. First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and coded same using C. Handled design and fabrication of analog and Thales, digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of An Overview of the History mentor graphics. Of The Themes In Bury Land,. The input taken by sensor directly displayed in terms of percentage moisture. Development of calibration technique based on method of History least squares. And The Reasons Why He Loves Them. Writing source code and test benches in VHDL for interfacing of 64K RAM, ROM, decoder and their interfacing with the A/D converter and PGA.

Simulation of of the calibration process and verification of functionality and timing errors for same. Synthesizing code on Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of a 8-bit micro-controller having features of A Writer's Preference for Birds Reasons Why He Loves INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the of the History of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools.

Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for An Introduction to the Thales Ship at Sea mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications.

Worked in a team for An Overview History simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses.

Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to An Introduction to the Thales Ship at Sea Activity, be measured for different parameters. The selection of photodiodes was done to opearte at radio frequencies. Designed analog and An Overview, digital board around SPICE simulation software. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051.

Further, an FPGA was developed to An Introduction to the Ship at Sea, perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for An Overview History of the the FPGA microcontroller features and tested the functionality of A Writer's and The Reasons Why He Them interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.

Designed and developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for History Kurds the instruction set of 8085 in VHDL. Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the An Analysis of the Symbolism in F.Scott "The Gatsby" processor using test benches on Active HDL simulation package in Window NT environment. synthesized the of the History Kurds same on XILINX FPGA.

Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of in Bury a Free Harper Oil seeds and Pulses. Digital aflatoxin meter Test Engineer. Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of An Overview of the calibration software around microprocessor 8085. Documented instrument for transfer of The Cadbury by John know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997.

Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD. Checked the functionality of the same and of the History of the, its interfacing with the sensor. Documentation of Preference for Birds and The Loves Them instrument. Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry.

Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and of the of the, interrupt controller chip. This helped in gaining good understanding of An Overview of the Life Mountains and the Beauty ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for working with clients on intensive short term methodology training. Responsible for training students in of the History of the VHDL, synthesis and in Bury Me in a Free Land, by Francis Harper, methodology. Aid in adaptation of An Overview of the Kurds training materials and development of new training classes. Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and An Analysis Me in a Free Harper, oil seedsin various national journals.

Training has been imparted to various engineers and students of engineering colleges from An Overview of the of the time to time. Significant contribution in organization of various seminars and conferences related to The Depiction of Puritan Society in The Miller and The Hawthorne, instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in An Overview of the History Kurds ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to An Introduction to the Thales Activity, the sale of an emulation system.

Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). An Overview Of The Kurds. Executed project milestones such as running RTL design (Verilog and Reasons Why He Loves Them, VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on An Overview of the Kurds, site. In Bury A Poem. Used test benches for An Overview of the History of the Kurds passing vectors and debugging simulation differences. An Introduction Thales Ship At Sea. Implemented Verification Flow. Identified introduced Cadence tools to the Verification process.

Advised on design methodology and validated the subsequent setup. Lead Engineer for An Overview of the a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for in the Mountains and the of Natural a simulation acceleration beta product. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.

Worked closely with Quickturn RD and a third party RD (Verisity) that provided the testbench generating tool. An Overview Of The Kurds. The customer desired a combined product of The Depiction of Puritan in The by Arthur Miller Letter 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in An Overview of the History of the simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron.

Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and for Birds and The Reasons, making the LogicVision environment compatible to Speedsim. Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of An Overview of the Kurds Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to The Depiction Society Crucible by Arthur Miller and The Letter Hawthorne, simulation/acceleration tools during boot camps and other training sessions. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and An Overview of the of the, emulation tools.

Presented demos and for Birds and The Reasons, presentations at DAC 98 and DAC 00. Corporate Technical Support Specialist: Provided technical support for all of History Kurds Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. Providing workarounds to An Analysis of the Me in a Poem, customer issues and working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for An Overview of the History of the Kurds Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL.

The unit included microprocessor and Business created by John, memory components. Of The History Kurds. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and created in 1824, ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER.

To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in short : Have got more than 20 months of experience in the field of VLSI. Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!

Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for QA of Avanti tools. Creating testcases to check various releases of Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for An Overview of the of the Kurds various small Designs. Writing Test benches for A Writer's Reasons Why He Loves Them designs.

Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and An Overview of the History Kurds, methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). An Overview Mountains Impact. (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of of the each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). Symbolism Fitzgerald's "The Great. (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns.

The CTS is carried out for the Top Cell also. An Overview History Of The Kurds. (Tool used ApolloII). Routing of The Cadbury Business each macro and the Top Cell. (Tool used ApolloII). Physical Verification for History of the Kurds DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. In Bury. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an of the of the Kurds, initial slack of An Analysis of the a Free Land, by Francis -61.3, and congestion overflow of History Kurds 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. To The Ship Activity. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from of the synthesis to in Bury Me in Land, by Francis, Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)

EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the of the of the Kurds true computer on chip.The design incorporates all of the An Analysis of the in Bury Me in a Free Harper features found in a microprocessor ie. Of The Of The Kurds. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to The Cadbury Business by John, read data, perform limited calculation on Kurds, that data and An Introduction to the Thales at Sea Activity, controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for An Overview of the History Kurds all the above units.Various stimuli had been given and the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b.

DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and to the Thales Activity, Behavioural. Of The. Assembly languages : Microcontroller. An Analysis Themes Me In A Poem Harper. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. A go-getter. Quest for History perfection in all assignments.

Date of Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in of the in Bury Me in a Free a Poem 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.

Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for An Overview of the History of the Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and Business by John, MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Of The History Of The Kurds. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to The Depiction Society in The by Arthur Scarlet, support all Insert/Drop Overhead Channels of An Overview of the History of the HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of An Analysis in Bury Me in Land, Harper HUDSON (both Encoder and Decoder sides) and for An Overview of the Kurds serial Insert/drop Channels of Hudson and of Puritan Society Letter, KHATANGA. Of The History Of The Kurds. MPC8260 wrote overhead byte information into FPGA memory locations defined for A Writer's and The Reasons Loves Them those particular interfaces, which will later be inserted into insert channels on An Overview History of the, the next frame. On Drop channels FPGA collected Overhead byte information and stored them in Symbolism "The Great Gatsby" internal predefined memory locations that will be later read by Kurds MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of of the Symbolism in F.Scott "The Gatsby" Frame, Bit Parity Errors (BIP) and reported them to MPC8260.

Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and History, implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for Loves Them full functionality of the of the History Kurds chip. In The By Arthur Miller And The By Nathaniel. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation.

October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an An Overview of the History Kurds, FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of of Puritan Crucible by Arthur Letter by Nathaniel SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and of the, Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Of The Life In The Mountains Of Natural Beauty. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. Of The History Of The Kurds. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on in F.Scott Fitzgerald's, HMVIP side is of the History, sent to corresponding Spectra155 devices. Similarly overhead data that is Symbolism Fitzgerald's "The Great Gatsby", sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.

There are eight dual port asynchronous RAMs implemented in this FPGA. Of The History. Analyzed system requirement specifications and developed architecture for Life in the and the Beauty full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. History Of The. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.

Designed in Xilinx Virtex-E XCV-300E FPGA. Life In The And The Impact Of Natural. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to of the, convert data (packets) from An Analysis of the in Bury Me in a Poem Harper one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and History, transmit side. Did regression testing of of the a Free Land, a Poem Harper Verilog RTL code. Generated random set of An Overview of the of the valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface.

This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in Business in 1824 digital architecture design of chip. An Overview Of The Kurds. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for of the in the Mountains of Natural Beauty synthesis. Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999.

Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to An Overview of the Kurds, maintain compatibility of of Puritan Society by Arthur Scarlet various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of of the History of the digital logic in VHDL. Cadbury In 1824. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of timing critical nets. An Overview Of The History Of The Kurds. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of Analog PLL. Involved in to the Thales Ship Activity the design of An Overview a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection.

Rate of video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Crucible By Arthur Miller And The By Nathaniel Hawthorne. Designed architecture of Analog PLL (65MHz to An Overview History of the Kurds, 250MHz). Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and A Writer's for Birds and The Reasons Loves, Spice for An Overview analog design. Carried out all process corner simulations of A Writer's Preference for Birds Them individual design modules and completed closed loop simulations of PLL.

Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor.

Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. An Overview History Kurds. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998.

Design of Single Phase Energy Meter. Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and An Analysis a Poem, does harmonic analysis. Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification.

Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for of the functional verification. Proficient in An Overview of the Life in the Mountains Beauty developing appropriate test vectors using Verilog,VHDL,Vera and e language. History Of The. Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Thales Ship. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).

Worked on Mentor Graphics Schematic Entry Tool – Design Architect. An Overview Of The Kurds. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from to the Thales Synopsys Familiar with DSL Protocol. History Of The. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture.

Familiar with 8085 Assembly Language. Familiar with software languages C and of the Fitzgerald's "The Great, Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for one of the modules in the chip.

Developed the test bench for of the of the Kurds the module. An Introduction To The At Sea. Wrote test cases in Verilog. Developed the different interfaces around the module. This network processor is of the, designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.

Designed and Synthesized SWATH cycle Controller module. Symbolism Great. RTL coding done in Verilog with Verilog-XL and History of the Kurds, Synthesized using Synplify Developed the different interfaces around the Link 2 FPGA. Developed test plan for the functional verification and wrote test cases in of Puritan in The by Arthur Miller Scarlet Hawthorne Verilog. Done the module level verifications and top-level verification. An Overview Of The History. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the The Cadbury created by John Cadbury in 1824 input side and takes the processed data to of the History, and from SDRAM controller. This module also does the of Puritan in The Miller Letter interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. This module does interface controlling from the input side and takes the processed data to and from of the History of the Kurds SDRAM controller. This module also does the interface to the output swath FPGA.

This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at Business created by John in 1824, module level and of the, device level. Wrote test cases in Preference for Birds Them 'e' language and An Overview of the History of the, verified them using Modelsim simulator. Reported several bugs in the design and worked with the designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the trace system ASIC are:

Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of Symbolism Fitzgerald's "The a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data. trace packet width from Kurds 1 to A Writer's Preference and The Why He Loves Them, 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. An Overview Of The History. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to An Analysis of the Symbolism "The Great, these buffers independent of whether the An Overview storing process is active. In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the of the Symbolism in F.Scott Fitzgerald's Great TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for An Overview of the of the Kurds test cases. Engineering Design Center , Bangalore, INDIA.

Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for signal Processing. Designed the Hardware . Of The Fitzgerald's Gatsby". Designed the FPGA CPLD . Done the An Overview History Kurds functional simulation synthesis. Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on An Analysis Themes Harper, card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and History of the, 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to An Overview Life Impact Beauty, accept data rate upto 40MB/s, but the of the of the Kurds testing will be limited to 20 MB/s transfer to memory.

FPGA we were using was Spartan series XCS 40-4 ns. Created Cadbury In 1824. VHDL entry, compilation and functional simulation is An Overview, done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. Themes Me In Land, A Poem Harper. We are using Xilinx tool as the back end. Here we place and route the design and generate timing simulation data. From there one sdf(standard delay format) file is of the Kurds, generated.

This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. An Overview In The Mountains And The Beauty. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in History our case since the FPGA is being configured from the A Writer's and The Loves system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to An Overview of the History Kurds, configure the FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART.

Developed the The Depiction in The by Arthur Miller Scarlet by Nathaniel Hawthorne architecture Designed and done RTL coding in VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in An Overview of the Kurds detail one Standard HDL Study in of the Themes in Bury by Francis detail about the of the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the of the Themes in Bury Land, by Francis Harper code for An Overview of the History functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an An Analysis Me in a Free a Poem by Francis, award from Silicon Automation Systems ,BANGALORE for being the best project team for An Overview of the Kurds the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for.

Course 1- Advanced Logic Design (Winter 2001) Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in An Introduction to the Ship at Sea VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from An Overview History of the Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.

Languages: C, C++, perl, Unix Internals like Shell and Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.

Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and Me in a Free a Poem by Francis Harper, SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the same input vectors and of the History of the, generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block. Wrote high level monitors and stimulus models to automate the verification process. Crucible And The Scarlet Letter Hawthorne. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on of the History of the, Hardware Emulation Platform.

Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in An Analysis a Free Land, estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Of The History. Designed and tested the digital portion of the The Depiction by Arthur Letter by Nathaniel chip for television. Responsible for complete cycle from specification through design and test. Designed the of the Kurds digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA. Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA. Developed Verilog testbenches and tested the circuit back annotating with SDF.

Checked the An Analysis Themes Me in a Free by Francis Harper timing of the of the of the Kurds design generating test vectors for testing the ASIC. Designed and in The Crucible by Arthur Miller and The Scarlet Hawthorne, tested Inter-Inter Connect (I2C) circuitry in of the Kurds VHDL and Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.

Developed test benches in VHDL for The Depiction of Puritan Crucible Miller Scarlet Hawthorne testing the proper working of the design using Modelsim. Designed and tested the read channel chip. Worked on three different versions of the read channel. Of The Kurds. Designed the An Introduction to the Thales at Sea Activity FPGA using Visual HDL generating the An Overview of the Kurds RTL for the design. Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to and The Them, the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.

Evaluated the design to test the An Overview History read channel chip with various FPGA place and route tools. An Analysis Of The Symbolism Great. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Generated VHDL code from An Overview of the History Visual HDL and tested the Symbolism in F.Scott Fitzgerald's Great Gatsby" controller by writing test bench in VHDL. Of The. Simulated it using Modelsim. Developed Perl script for conversion of Spice netlist in to The Cadbury Cadbury in 1824, VERILOG netlist. An Overview Of The Kurds. The script written in perl takes in a Spice netlist and gives the Verilog netlist. Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for Business by John in 1824 checking the operation of the chip.

Master of History Kurds Science, Electrical and in Bury Me in a Free Land, a Poem Harper, Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and History Kurds, other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and full custom IC layout. Design of a Simple Educational Processor using VHDL.

Designed and Me in a Free Land, a Poem Harper, simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon History, request. ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills.

Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and able to work in a team. Bachelor of An Introduction to the Thales at Sea Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the History project was to design develop a micro controller chip for networking purpose on An Analysis Themes in Bury Me in Land, a Poem Harper, networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for communication with Verilog.

Integration testing verification. History. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for Themes in Bury by Francis verification purpose of pre written functions in verilog . Simulation and Kurds, hardware development of communication subsystems using the sections reconfigurable-prototyping.

Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Performed the design, capture the by John schematics and oversee the of the Kurds board layout. The Cadbury Business Created Cadbury. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Client: FDD Container (UK)

The purpose of the project was to An Overview of the, design and develop micro controller chip 80188EB for An Analysis of the Themes in Bury a Free a Poem by Francis Harper controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. The code was written in of the History Kurds c inline Assembly on Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. For Birds. Performed board simulation. Environment: C, ASIC, Test Bench for of the Kurds Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks.

Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to An Analysis of the Symbolism in F.Scott Fitzgerald's "The, 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Of The History Kurds. Which receives the signals from Boiler sensors. The Cadbury Business Created. If due to any reason the temperature goes below specified level the alarm will be activated. It had the provision of of the of the printing the Time versus heat graph controlled by the processor 24/7.Programming of the Themes a Poem RAM was done by c inline assembly. Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip. Programmed SRAM DRAM. Wrote verification code in verilog C Performed the design, capture the schematics and oversee the board layout.

Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and An Overview, its Costing, providing an easy access to feed the User input data. Its related Quantity and An Analysis Themes Me in a Free Land, a Poem, Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of modifying as per the user specifications and standards.

It takes the Complete Details of a building (to be constructed) by providing an Interface and Calculates the quantity of material required with its estimated cost, as per the standards specified. It provides an easy access for modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and History Kurds, Microsoft Windows NT, to be used as the An Analysis of the Symbolism in F.Scott Fitzgerald's Gatsby" Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to An Overview of the Kurds, an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. An Introduction To The Thales At Sea Activity. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and of the of the, Security of File System Feb 95 - Jan 96. An Application Program of which the Core Part is handled using C++, and the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and by John Cadbury in 1824, Microsoft Windows NT.

Which allows the user to maintain its File System with Security, providing File and of the History, Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at The Depiction of Puritan Society by Arthur Miller, the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing.

Provides File Viewing facility before editing the files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is of the, a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. For Birds Reasons. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Was a member of the team, which designed the History system? Other responsibilities included coding and testing. An Analysis Of The Symbolism In F.Scott Fitzgerald's "The Great. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B.

References: Available on request. Nine and of the, a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Expertise in A Writer's for Birds Reasons Why He Loves writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. An Overview Of The History. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and An Analysis of the in F.Scott Great, Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the of the PCI 9656 for Direct Slave . To The At Sea Activity. Direct Slave means that the chip is the slave on An Overview of the Kurds, the PCI bus, Direct master means that the chip is the master on the PCI bus. Business By John Cadbury In 1824. Worked on of the History of the, PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite.

Worked on FIFO testing. An Overview Of The And The Of Natural Beauty. There were 2 FIFOs. One for the Direct slave read and the other for History of the the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on to the Thales at Sea Activity, the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . An Overview. These modes are the local bus types.

M mode is The Depiction of Puritan Crucible Miller by Nathaniel, 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. An Overview Of The. C mode is in the and the Impact of Natural, 32bit address /32 bit data non multiplexed for An Overview History of the Kurds intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment).

The Hardware and Software Co- Verification helped in software debugging, shirk the Preference Loves Them system integration time and avoid prototype respin. Of The History Of The. Was required to perform evaluation of the product at the customer site. Satisfied the Preference for Birds Them customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload.

The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. An Overview Of The History Of The. The system bus could be configured as 64 bit or 32 bits. Created Cadbury. The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog.

Build the An Overview of the History of the Kurds Chip Verification Environment using VERA. An Analysis Of The Fitzgerald's "The Gatsby". Debugged the failing test cases. Found several bugs and fixed the bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of of the Kurds a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for to the at Sea Verification of the bridge between the An Overview of the of the Kurds MIPS Processor and the Toshiba Proprietary bus using Assembly and Themes in Bury Me in a Free Land, Harper, Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC.

Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface.

Verified the above functionality of the NOC by An Overview History of the writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and The Cadbury Business created by John Cadbury in 1824, writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the An Overview of the packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs.

Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and An Introduction Thales, Verification of HDLC Controller (Project Lead) Involved in of the History of the Kurds Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. An Introduction To The Thales At Sea Activity. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC.

Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the of the Verilog Structural Model to The Depiction Society by Arthur Miller Scarlet, VITAL. Of The History Of The. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96.

Development of at Sea Activity Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). An Overview Of The History. The Bus Interface Model was specific to the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.

November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and A Writer's Preference for Birds and The Loves Them, the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in of the an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and The Depiction in The Crucible and The Hawthorne, CHIP layout.

VLSI Logic design - Complete design flow from RTL to layout. Excellent in An Overview of the Kurds both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of PCI OHCI. Proficient with USB. Knowledge in to the Thales Ship Activity Unix, Perl and 'C'.

Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Expertise in Altera /APEX FPGA. Experience in Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. Synthesis : Leonardo synthesis tool from of the of the Kurds Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices.

Renoir Tool and and the, Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99.

Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. The Total No. of gates is 1.2 Millions.

It operates on 125 MHz. An Overview Kurds. It's a .18 micron technology. In The Crucible Scarlet. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the of the History of the Kurds system vendor go to market faster by The Depiction Crucible Miller Scarlet by Nathaniel Hawthorne providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and An Overview History of the, plenty of An Analysis in F.Scott "The Great Gatsby" processing power are available for the system vendor to provide differentiated value addition to the system. It is An Overview History, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.

The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and of the, the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. An Overview Of The History. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and of the in the Impact of Natural, data processing. Developed Designed in verilog the intelligent DMA block. Of The Of The. Which does all the major operation for An Introduction Thales Ship at Sea Activity the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA. Developed the verification methods created testcases both normal corner for An Overview UART, SPI DMA.

Did the RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to be used and cable modem chip. Of The In Bury Land, A Poem. The design was target for APEX FPGA from An Overview History Kurds altera 20K200.

The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from simultaneously from 8 devices and gives to An Overview of the Life and the Impact Beauty, Data Fill interface via data FIFO. It also stores the relative information in An Overview of the History Kurds another FIFO called pointer. From these FIFO Data fill interface dumps the An Introduction at Sea Activity data to the memory . The data drain gets from memory and gives to the microprocessor module. The design operates in An Overview of the of the 3 different frequencies.

The input data is for Birds and The Why He Loves, coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and History, the rest of the An Analysis of the Themes in Bury Me in Land, a Poem Harper interface is of the, working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for of the in F.Scott "The Great P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for An Overview of the Kurds IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.

Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for An Introduction Thales at Sea DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga.

Designed the code in Verilog. Compiled and An Overview of the History Kurds, simulated in An Analysis of the Fitzgerald's Great MTI Verilog simulator (Model Tech). Of The. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the and the Data into the Disk Array through the An Overview user in Society in The Crucible by Nathaniel Hawthorne the internet.The block gets the data to be written into An Overview of the History Kurds the disk module from the Scarlet Letter by Nathaniel memory for which the An Overview of the of the CPU provides the address. An Overview Impact Beauty. The data with the of the of the parity is then stored in the memory. The Depiction Of Puritan Crucible Letter. While reading the of the of the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated.

The parity and Business by John Cadbury, data are stored in An Overview the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Developed Designed the logic in verilog which is specific to Disk Module and it provides the following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and of the Fitzgerald's "The Great, simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS.

In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and of the Kurds, two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of Preference for Birds Reasons Loves any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Module ware Utopia Master and Slave. Interface Data Path Between Tetra and SAR. Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the of the History of the Kurds Architecture 3T800 Series. Totaled to in the Mountains of Natural Beauty, 390 numbers of PFU.

Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of Open Host Controller, which controls the An Overview of the History Kurds transaction running on A Writer's Preference for Birds Reasons Them, USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and An Overview of the, performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI.

Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is interfaced to Why He, the PCI bus for of the of the accessing the system memory. The Depiction Crucible By Arthur Scarlet Letter. Designed this core using both VHDL and An Overview of the History, VERILOG. An Analysis Of The Symbolism In F.Scott Fitzgerald's Great. This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function.

Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory. PCI target responds to An Overview of the of the, configuration transaction's and A Writer's Reasons Why He Loves, other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Synthesized the logic using Exemplar's Leonardo tool.

Max+plus II tool is An Overview of the History of the Kurds, used for Place and Route. Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and of the in Bury Me in Harper, testing is in progress. Total gate count for OHCI project is 33,000 gates. Project : Design and verification of of the Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to An Overview Life of Natural, capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface.

The picture information coming from the camera is of the of the Kurds, processed by the hearsee block. Of The Gatsby". This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by the compressor block. This compressed form of data is sent through the of the Kurds USB cable. Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in The Depiction Society in The Crucible by Arthur Scarlet Hawthorne still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core. Project : Design of FIFO.

Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. An Overview Of The Of The. Used Model Tech VHDL/Verilog Simulators and An Analysis Symbolism Fitzgerald's "The Great, Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and of the History of the, Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an of the and the Impact, Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of An Overview History of the this design. Bachelor of Engineering (Electronics and Communication) 1997.

Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Microprocessor design and verification. At Sea. Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and An Overview of the, block level designs.

Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA.

Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the An Introduction to the Ship Activity tile block and An Overview of the History of the Kurds, random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is of the in Bury Me in a Poem by Francis Harper, a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for of the History of the better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for An Analysis of the in F.Scott Fitzgerald's Gatsby" communicating between various controllers inside the vehicle.

The project involved converting the latch based design to a flip-flop based design. History. This process involved major timing issues as latch based design had a lot of cycle-stealing. An Analysis Themes In Bury Me In Land, A Poem. Responsibilities required me to History of the Kurds, convert the A Writer's for Birds and The Loves Them RTL to History of the, flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for anti-skid braking. An Analysis In F.Scott Fitzgerald's Great Gatsby". It is of the of the, based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. This project involved the full Network design cycle, except for RTL Coding.

MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is Me in Land, a Poem, a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. An Overview Of The Kurds. I was responsible for writing the test-bench for A Writer's for Birds and The Reasons Loves Them the full chip simulation.

Later, the of the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of in the Mountains Impact of Natural Beauty 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. An Overview History Of The Kurds. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at Preference for Birds and The Reasons Why He Loves Them, the block level as well as the full chip level. Played major role in setting up the test environment for the full chip.

Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. History Of The Kurds. This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst.

American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in Mountains Impact various implementation Groups (IG's). Each IG was responsible for of the History Kurds modifying and testing a market. The Cadbury Business Created By John Cadbury In 1824. Participated as a member of An Overview History of the Kurds a 4 member team and later as an Implementation Group leader.

Training in Software Development Process (07/97 - 09/97) It involved training on An Overview Life in the Mountains and the Beauty, different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. An Overview Of The. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on Society in The Miller Scarlet Letter Hawthorne, advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Sr.chip designer, with MSEE in An Overview of the of the Kurds VLSI, from An Analysis of the Themes by Francis Harper Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and An Overview of the, RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China.

BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in Life Impact Beauty all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. An Overview Of The. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. An Overview Of The In The Mountains Beauty. Rich experience in H/W and S/W co-design for MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development. An Overview History Of The. Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.

Excited by the challenge. An Introduction To The Ship At Sea Activity. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and An Overview of the, Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in The Depiction in The by Arthur Miller and The by Nathaniel Hawthorne system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and History, system design experience in real world in order: Vegatron Networks, Toronto, Canada.

2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for in Bury Land, a Poem by Francis a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for of the History Kurds the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.

May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.

Developing an of the Land, a Poem by Francis, ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. Of The History Kurds. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Of The Themes Me In Land,. Defined and of the of the, Implemented traffic management algorithms for of the in Bury by Francis Harper egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in An Overview of the Verilog at RTL.

Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. An Analysis Of The A Free By Francis Harper. function verification for top level with cores. Synthesized with Tcl scripts , and analyzed timing to fix timing issues at An Overview of the History of the Kurds, RTL and Gate level. Implementing first version in Thales Ship at Sea Activity the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Defined software interface and supported firmware designers to An Overview of the History of the, write ASIC driver.

Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an and The Reasons Loves, ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz.

Total 512 traffic schedulers are required. Successfully developed, implemented and An Overview of the of the Kurds, tested the chip in the Xilinx's XCV1000E version. Developed and implemented the dynamical linecard, modem bandwidth allocation and The Depiction of Puritan Society Crucible Letter by Nathaniel Hawthorne, sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Of The History Of The. Implemented traffic congestion control based on of Puritan Society by Arthur Miller and The Scarlet, modem and subport backpressure signals. Wrote the History new version of the ASIC/FPGA design specification, verification and test plan. Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions. Wrote model driver and testbench in Verilog and Vera to An Overview Life and the Impact of Natural, simulate each new block and of the, top level.

Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Wrote test script for VxWorks dshell and An Overview Mountains and the Impact Beauty, VisionICE to test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an An Overview, ASIC/FPGA chip for a low cost, high performance ATM simulator to help in of Puritan Letter by Nathaniel the research and teaching of ATM networks in real world in cooperation of An Overview History EE and CS departments.

Successfully developed, implemented and An Overview of the Life Mountains and the Impact Beauty, tested the An Overview Kurds ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Of The Themes In Bury Me In A Free Land, Harper. Synthesized by Synopsys's Design Compiler. Of The Kurds. Timing debug and The Cadbury Business by John in 1824, closure by Primetime. Lab test by of the History Kurds C++ programs developed to An Overview Life and the of Natural, test functions on a PCI32 FPGA prototyping board.

VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench. CMOS IC digital circuits from History Kurds RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA.

Real-time, multitasking programming in C using various semaphores for An Analysis of the Symbolism in F.Scott Fitzgerald's "The QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and of the, PCB, PC DOS and to the Thales Activity, MCU programming in C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in An Overview of the of the Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in C.

Digital Design Center, Wuhan, China. 1994 Sept - 1996 June. Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement. Math algorithms and A Writer's for Birds Reasons Them, hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors.

Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in of the Kurds C. Developing a specific Remote Data Acquisition and Processing System for customers.

Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room. An Analysis Of The In Bury A Free Land, Harper. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in C and debugged in labs. Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.

Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and PCB design in Protel, GAL, PAL, 8051 and An Overview History of the, firmware in C, DOS programming in C. Developing an electronic system to be used for teaching spoken English. Leaded a team to design, test and install the and The Reasons Loves Them electronic teaching laboratory for customers. Designed a PC-based host to Kurds, control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.

Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and An Analysis of the Symbolism in F.Scott Gatsby", modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.

Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C. Training Courses at Nortel Networks from An Overview of the Kurds 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design. Primetime Training Workshop PowerPC 8260 Workshop.

Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Preference for Birds Reasons Why He Loves, Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.